PATENTS

Theta has developed the following patents:

Patent # 7,010,330 Power Dissipation in Wireless Transceivers

Methods and circuits for reducing power dissipation in wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current reduction, impedance scaling, and gain changes either separately or in combination to reduce power dissipation. For example, bias currents are reduced in response to a need for reduced signal handling capability, impedances are scaled thus reducing required drive and other bias currents in response to a strong received signal, or gain is increased and impedances are scaled in response to a low received signal in the presence of no or weak interfering signals.

Patent # 7,049,875 One-Pin Automatic Tuning of MOSFET Resistors

Methods and apparatus for automatic tuning of MOSFET resistors providing accuracy and linearity throughout process and temperature variations. In accordance with the methods, the source and drain of a MOSFET device are biased in a balanced manner around a common mode voltage using a circuit controlling the gate voltage of the MOSFET to set the current through the MOSFET responsive to the value of a resistor. Operating MOSFETs, such as in MOSFET-C filters, with the same device conductivity type, gate bias, substrate voltage and signal common mode voltage provides linear MOSFET resistors, accurately set by a single resistance value. Use of an external resistor provides a single pin setting of MOSFET resistances, that may be independent of temperature and process variations. Various embodiments are disclosed.

Patent # 7,075,377 Quadrature Voltage Controlled Oscillators with Phase Shift Detector

In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated `I` and `Q` channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Patent # 7,155,185 Apparatus and Methods for Eliminating DC Offset in a Wireless Communication Device

Apparatus and methods for eliminating DC offset in a wireless communication device operable on a continuous basis or on a sampled basis. In a receive channel, the output of a forward variable gain amplifier is fed back to an RC circuit to charge the capacitor (C) to a voltage dependent on the DC offset in the variable gain amplifier output. The voltage on the capacitor is amplified and summed with the input to the variable gain amplifier. The RC circuit is configured to provide a high gain feedback at DC and very low frequencies, but very low gain at signal frequencies. Preferably the output of the forward variable gain amplifier is fed back to the RC circuit with a gain that is inversely proportional to the forward gain. Disconnection of the capacitor and feedback of the capacitor voltage provides sampled operation. Various embellishments and sample applications are disclosed.

Patent # 7,253,712 Integrated High Frequency Balanced-to-Unbalanced Transformers

Integrated high frequency balanced-to-unbalanced transformers suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the primary and secondary inductors for the minimization of capacitive effects between layers while using a minimal number of metal layers. Two solutions are provided, one having embodiments with a symmetrical primary inductor in a 4-metal layer implementation and one having embodiments with a non-symmetrical primary inductor in a 3-metal layer implementation.

Patent # 7,268,627 Pre-Matching of Distributed and Push-Pull Power Transistors

Pre-matching of distributed push-pull and power transistors enabling the effective use of high-power and high-frequency transistor arrays. In accordance with the invention, a pre-matching element is connected between stages of multi-transistor arrays. The pre-matching element serves to transform the impedance at a connecting point between stages toward an impedance level that is less sensitive to transmission line losses. In one embodiment of the invention the pre-matching element is a shunt inductor.

Patent # 7,271,622 Quadrature Voltage Controlled Oscillators with Phase Shift Detector

Patent # 7,286,015 Linear-in-dB Variable Gain Amplifiers with an Adaptive Bias Current

Linear-in-dB current-steering VGAs with an adaptive bias current operable so that as the gain of the amplifier decreases, the DC current consumption also decreases. The modified VGA circuits result in power consumption savings, which are of particular value in wireless (battery powered) applications.

Patent # 7,372,925 Wireless LAN Receiver with I and Q RF and Baseband AGC Loops and DC Offset Cancellation

A wireless local area network receiver having separate automatic gain control (AGC) loops for providing a radio frequency AGC and a baseband frequency AGC, as well as a DC offset cancellation circuit. The AGC loops control a low noise amplifier amplifying the received RF signal, and the baseband signal or signals from a mixer of I and Q mixers. The DC offset compensation loop is also responsive to the baseband AGC signal to maintain a substantially fixed gain in the DC offset compensation feedback. Details of various embodiments are disclosed, including embodiments for orthogonal frequency division multiplexing (OFDM) that provide the AGC operation and the DC offset cancellation to the desired levels within the relatively short period of a preamble that precedes the data transmission.

Patent # 7,489,192 Low-noise Amplifiers

A low-noise amplifier, that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance, is shown. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without Noise Figure degradation.

Patent # 7,499,687 Wireless Transmitter DC Offset Recalibration

In many circuits, including those operating in radio frequency (RF), there is commonly a need to perform DC offset cancellation. The DC offset is an error in an output signal in respect to the input that may cause a circuit to enter into undesirable or non-tolerable conditions of operation. While in most cases a static solution is provided the use of an analog loop may be inappropriate because of the adverse impact on speed. By adding a fast feedback loop finely impacting the adjustment of an amplifier, both the initial calibration is achieved as well as a recalibration of the system.

Patent # 7,546,332 Apparatus and Methods for Implementation of Mathematical Functions

Apparatus and methods for implementation of mathematical functions apparatus providing both speed and accuracy. Disclosed are specific circuits and methods of operation thereof that may be used for the purpose of implementing an exponential function, a squaring function, and a cubic function, using the same basic circuit. By applying a desired weighting function on a current source, an output current provides a value that corresponds exactly to the desired mathematical functions at discrete points, and closely tracks values in between the discrete points. The precision is defined by the selection of a voltage reference for the circuit. Various embodiments are disclosed, as well as embodiments implementing other exemplary functions.

Patent # 7,554,397 Highly Linear Low-Noise Amplifiers

A predistortion method for CMOS Low-Noise-Amplifiers (LNAs) to be used in Broadband Wireless applications is presented. The method is based on the nulling of the third order Intermodulation distortion (IMD3) of the main amplifier by a highly nonlinear predistortion branch. Maximum third order product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and Noise Figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3 dB improvement in the Input Third-Order Intercept Point (IIP3) with a reduction of only 1 dB and 0.44 dB in amplifier gain and NF respectively.

Patent # 7,702,045 Method for Estimating Wireless Channel Parameters

Method for the estimation of channel parameters in a wireless communication system. In accordance with the method several levels of the wireless channel parameters estimation take place to address the specific requirements of the channel. Based on the level of estimation required an appropriate estimation algorithm is selected to achieve the desired results. The evaluation of the channel state and thereafter determining the appropriate parameter estimation requirements provide for a superior overall performance of the wireless system.

Patent # 7,808,356 Integrated High Frequency BALUN and Inductors

Patent # 8,183,970 Integrated High Frequency BALUN and Inductors

Application # 8,275,338 A Passive High-Frequency Image Reject Mixer

The apparatus is a complete passive implementation of an image reject mixer (IRM) that is capable of operating at very high frequency. Using a hybrid as part of the IRM circuit enables operation at very high frequencies that also employs a high intermediate frequency (IF). All the components of the design are passive and implementable in MOS technologies providing significant cost and implementation advantages. Furthermore, the apparatus is operative at frequencies that are higher than several tens of GHz.

Patent # 8,331,896 A Method of Operation of a Passive High-Frequency Image Reject Mixer

A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is operative according to the disclosed method. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM. Operative at a radio frequency (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF- signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO- signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO- signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.

Patent # 8,505,193 Method for manufacturing an on-chip BALUN transformer

Integrated high frequency balanced-to-unbalanced transformers and inductors suitable for operation in high frequencies, such as radio frequencies. Embodiments disclosed give consideration to issues related to the layout of the top and bottom inductors for the minimization of capacitive effects between layers and methods of manufacturing thereof. The manufacturing process comprises forming of a first winding in a first metal layer; forming an insulating layer over at least the first metal layer; forming of a second winding in a second metal layer such that the second winding path has both a vertical and a horizontal displacement to the first conductive path, preferably with an overlap that is less than a full overlap; and forming shunts to ensure continuity of each of the first and second windings.

Patent # 8,805,316 Method of manufacture of a passive high-frequency image reject mixer

A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is manufactured in a variety of silicon processes. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM, operative at radio frequencies (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF− signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO− signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO− signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM.

Patent # 9,031,525 Method of manufacture of a passive high-frequency image reject mixer

Patent #9,331,728 Power Dissipation Reduction in Wireless Transceivers

Patent #9,838,962 B2 Power Dissipation Reduction in Wireless Tranceivers

Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices with wireless receivers is disclosed. Embodiments provide for variably changing the bias current, impedance, and gain through a plurality of values, either separately or in combination, during receiver circuit operation to optimize power dissipation. The dynamic changes to gain, bias and impedance characteristics of the receiver circuit may occur in any of an amplifier, a filter, and a mixer, and are responsive to the components of an input signal comprising a desired signal and interferer signal. Dynamic changes may also be made to a dynamic range and noise floor of the receiver circuit.

Patent #9,838,962 Power Dissipation Reduction in Wireless Transceivers
Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices with wireless receivers is disclosed. Embodiments provide for variably changing the bias current, impedance and gain through a plurality of values, either separately or in combination, during receiver circuit operation to optimize power dissipation. The dynamic changes to gain, bias and impedance characteristics of the receiver circuit may occur in any of an amplifier, a filter, and a mixer, and are responsive to the components of an input signal comprising a desired signal and interferer signal. Dynamic changes may also be made to a dynamic range and noise floor of the receiver circuit.

Patent #10,129,825 Power Dissipation Reduction in Wireless Transceivers
Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices using wireless transceivers is disclosed. Embodiments of the present invention provides for dynamically changing the bias current, impedance and gain, either separately or in combination, during circuit operation to optimize or reduce power dissipation. The dynamic variations of gain, bias and impedance characteristics of mainly the receiver circuit are responsive to the components of an input signal comprising a desired signal and an interferer signal. The dynamic variations may be implemented by varying the value of a resistance and/or a capacitance by opening switches across one or more portions of the resistance. Also, the dynamic variations may include setting any of the gain, bias current, or impedance parameters of the receiver circuit in between a high and low level, followed by adjusting the parameter up or down in response to a desired signal and an interferer signal.

Patent #10,524,202 Power Dissipation Reduction in Wireless Transceivers

Processes, methods and circuits for improving battery life by reducing the battery power-drain of battery-powered devices using wireless transceivers is disclosed. Embodiments of the present invention provides for dynamically changing the bias current, impedance and gain, either separately or in combination, during circuit operation to optimize or reduce power dissipation. The dynamic variations of gain, bias and impedance characteristics of mainly the receiver circuit are responsive to the components of an input signal comprising a desired signal and an interferer signal. The dynamic variations may be implemented by varying the value of a resistance and/or a capacitance by opening switches across one or more portions of the resistance. Also, the dynamic variations may include setting any of the gain, bias current, or impedance parameters of the receiver circuit in between a high and low level, followed by adjusting the parameter up or down in response to a desired signal and an interferer signal.

Patent (Application 16/714,629 ) Power Dissipation Reduction in Wireless Transceivers